Papoutsakis S, Mansouri N. A Higher-Level Synthesis Tool for Rapid-Prototyping of Verilog RTL Designs from FSMD Specifications. J Stud Res [Internet]. 2021Nov.30 [cited 2025May17];10(4). Available from: https://www.jsr.jofsr.org/index.php/path/article/view/1440